What is Aaryan Oberoi?
Aaryan Oberoi is a device engineer and data scientist at Intel in Hillsboro, Oregon, focusing on the device physics of advanced Silicon CMOS. His work spans front-end-of-line transistor development, middle-of-line processes, and backside power delivery for advanced CMOS nodes. He earned a Ph.D. in Engineering Science and Mechanics from Penn State in 2024, with earlier research on 2D and 1D channel materials conducted during a stint at TSMC.
What does the website present?
The website serves as a curriculum vitae presenting his education, professional experience, and published work. It includes a résumé titled 'Doc. AO—2026 Rev. 3.5' and lists his specialization in FEOL transistor development, middle-of-line, and Backside Power Delivery. The site also details his channel materials expertise in Si CMOS (FinFET, GAA) and WSe₂ / MoS₂.
What are his main areas of specialization?
Aaryan Oberoi works on the device physics of advanced Silicon CMOS at Intel, spanning front-end-of-line transistor development, middle-of-line, and backside power delivery. He also focuses on 18A scribe-line Etest infrastructure and 1T1C embedded DRAM on FinFET. His published work includes papers in venues such as IEDM, Nature Electronics, Nature Communications, Nature Nanotechnology, and ACS Nano.
What are his notable affiliations?
He is a Diefenderfer Fellow at the College of Engineering from 2022 to 2023. He also served as Chairperson of the IEEE Student Branch at Amrita Vishwa Vidyapeetham from 2018 to 2019. These roles highlight his academic and professional affiliations.
What is his educational background?
His education includes a B.Tech. in Electronics and Communication Engineering from Amrita Vishwa Vidyapeetham in Bangalore, India, from 2015 to 2019. He also holds a Ph.D. in Engineering Science and Mechanics from Pennsylvania State University, University Park, PA.
What is his work on 1T1C embedded DRAM?
The website states his work on 1T1C embedded DRAM on FinFET, which is a denser, lower-leakage alternative to standalone DRAM for on-die memory at advanced nodes. This technology uses one transistor and one capacitor per cell.
What is his work on 18A scribe-line Etest infrastructure?
He is currently working on 18A / 18A-P scribe-line Etest infrastructure at Intel from 2024 to 2025. This involves building Etest data infrastructure and layout automation for target generation across Intel's 18A and 18A-P technologies.
What is his work on backside power delivery?
The website mentions his work on backside power delivery on Intel's PowerVia technology. This involves moving power off the frontside entirely and routing it through the wafer backside instead, which lowers IR drop and frees up frontside tracks for signal-only routing.
What is his work on front-end of line, advanced CMOS node 2026?
The website mentions his work on front-end of line, advanced CMOS node 2026. He is a device representative for the front-end of line on an advanced CMOS node, driving process and integration decisions across the transistor module.
What is his work on 18A-P scribe-line Etest infrastructure?
The website mentions his work on 18A-P scribe-line Etest infrastructure. This involves serving as the device-side interface to the Product Engineering team, defining what geometry and layout are needed for the next process step.
How is Aaryan Oberoi rated on Trustburn?
On Trustburn, Aaryan Oberoi has a rating of 3.6 out of 5 based on 5 reviews.
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